The present invention relates to semiconductor component arrangements and in particular to isolation techniques for such arrangements.
Two main methods exist today for achieving isolation of an Integrated Circuit (IC) component on a chip: junction isolation and Silicon on Insulator (SOI).
In the junction isolation technique, a reverse voltage is applied from the component to a surrounding isolation area and to the substrate. Normally the substrate and the isolation are connected. This technique has several drawbacks, such as leakage currents to the substrate, and the formation of parasitic transistors. Also, the higher the voltage of the components, the thicker the epitaxial layer must be. Since the isolation area must extend through the whole epitaxial layer, for high-voltage components, the isolation areas also become wide, making the component as a whole unnecessarily large.
In SOI technology the components are placed on an insulating oxide layer and are isolated from each other by means of trenches. This reduces the size of the component compared to junction isolation techniques by up to 50%, sometimes even more. The main drawbacks are the price of the SOI wafer as a starting material and the thermal insulation caused by the oxide layer. The thermal insulation results in a higher temperature of the component, which may affect the life span of the component, and there is a risk of the components being destroyed in thermal runaway.
A third method is to apply isolating trenches to bulk silicon. In low-voltage applications this method is used to save space or to improve the frequency performance of the components. The trench walls are usually covered by an insulator such as an oxide, and the rest of the trench is filled with polysilicon.
For high-voltage components of this kind the breakdown voltage tends to be too low.
It is an object of the present invention to improve the performance of high voltage semiconductor components using trenches on bulk silicon.
This object is achieved according to the invention by an arrangement in a semiconductor component including a highly doped layer on a substrate layer and is delimited by at least one trench extending from the surface of the component through the highly doped layer. A sub-layer between the substrate layer and the highly doped layer is doped with the same type of dopant as the buried collector, but to a lower concentration.
The object is also achieved according to the invention by a method of manufacturing a semiconductor component comprising a highly doped layer on a substrate layer, comprising the steps of
doping a sub-collector layer in the substrate layer,
doping a buried collector in the substrate layer using the same type of dopant as in the sub-collector layer,
forming at least one trench in the component, said trench extending from the surface of the component into the substrate layer.
Alternatively, the method may comprise the following steps:
epitaxially growing a sub-layer on a substrate layer, said sub-layer being lightly doped with the opposite type of dopant of the substrate layer,
epitaxially growing a highly doped layer on the sub-layer,
etching at least one trench in the component, said trench extending from the surface of the component into the substrate layer.
The sub-layer causes a more even distribution of the potential lines in the substrate and in the sub-collector layer, thereby avoiding areas of particularly dense potential lines. Since the breakdown voltage is lower in areas with dense potential lines, avoiding too dense potential lines means increasing the breakdown voltage of the component.
The term xe2x80x9ctype of dopantxe2x80x9d refers only to n-type or p-type, respectively. The actual dopant used in the highly doped layer and the sub-layer does not have to be the same.
Preferably, the highly doped layer is a part of the collector covered by a lightly doped epitaxial layer. Areas to form the bipolar components, such as a base, a collector and an emitter may then be formed in the epitaxial layer. In the same way, MOS components or diodes could be formed using the buried layer as a part of the drain or the anode, respectively. If the highly doped layer is at the surface of the component, and does not cover the whole component, it may be used as the source and drain of a lateral MOS component, or a diode may be formed.
A suitable top concentration of the dopant used in the sub-layer lies in the range of 5xc2x71015 ions/cm3-1017 ions/cm3. A preferred depth of the sub-layer is between 2 xcexcm and 10 xcexcm below the highly doped area, that is, the distance from the depth where the sub-layer dopant begins to exceed the collector doping profile down to the pn junction between the sub-layer and the substrate layer is preferably between 2 xcexcm and 10 xcexcm.
The semiconductor component according to the invention preferably comprises an area doped with the opposite type of doping of the highly doped layer, surrounding the bottom of each trench, but not in contact with the sub-collector layer.
This area is introduced to increase the threshold voltage to avoid the forming of leaking parasitic MOS components by the n+-doped buried collector layer on both sides of the trench.
The polysilicon should have approximately the same potential as the substrate so that there will be no leakage currents from the parasitic MOS transistor. To achieve this, the trench walls may be covered with an oxide layer and the interior of the trench is filled with polysilicon, the polysilicon being in electrical contact with the substrate layer. Electrical contact between the polysilicon of the trench and the substrate layer may be achieved by means of a surface contact, or by a hole in the oxide layer at the bottom of the trench. Alternatively, the polysilicon in the trench and the substrate layer may be connected to the same potential outside the chip.
Suitable dopants for the highly doped layer are arsenic or antimony, which are slow diffusing dopants.
A suitable dopant for the sub-layer is phosphorus, which is a fast diffusing dopant. If a fast diffusing dopant is used, the sub-layer may be doped at the same time as the highly doped layer, or before, or even after, it.
Arsenic or antimony may also be used as the dopant in the sub-layer. In this case the sub-layer may be doped before the highly doped area, since the dopants for the sub-layer have to diffuse further into the substrate.
It is feasible to connect the trench delimiting the component to at least one other trench delimiting at least one other component. In this way, if surface contacts are used to make the potential of the trench close to the potential of the substrate layer, all the trenches can be kept at the low voltage using a minimum of contacts.